Thermal-aware floorplan schemes for reliable 3D multi-core processors

Authors:
Dong Oh Son;Young Jin Park;Jin Woo Ahn;Jae Hyung Park;Jong Myon Kim;Cheol Hong Kim
Affiliations:
School of Electronics and Computer Engineering, Chonnam National University, Gwangju, Korea;School of Electronics and Computer Engineering, Chonnam National University, Gwangju, Korea;School of Electronics and Computer Engineering, Chonnam National University, Gwangju, Korea;School of Electronics and Computer Engineering, Chonnam National University, Gwangju, Korea;School of Electrical Engineering, University of Ulsan, Ulsan, Korea;School of Electronics and Computer Engineering, Chonnam National University, Gwangju, Korea
Venue:
ICCSA'11 Proceedings of the 2011 international conference on Computational science and its applications - Volume Part II
Year:
2011

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Abstract

Interconnection delay has become a critical problem in performance improvement of 2D multi-core processors. 3D integration technology can be a good solution for reducing the interconnection delay in multi-core processors. However, the 3D technology magnifies the thermal challenges in multicore processors. For this reason, the 3D multi-core architecture cannot be practical without proper solutions to the thermal problems. Architecture-level thermalaware approaches such as dynamic thermal management (DTM) reduce the peak temperature in the processor by sacrificing the performance. On the other hand, thermal-aware design techniques using floorplan lead to peak temperature reduction with minimal performance degradation. This paper investigates how the floorplan schemes handle the thermal problems in 3D multi-core processors. First, we propose two kinds of foorplan schemes for reducing the temperature on integer register and load store queue, respectively. And then, we propose the thermal-aware floorplan schemes by combining these two kinds of floorplan schemes.