Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
WCDMA for UMTS: Radio Access for Third Generation Mobile Communications
WCDMA for UMTS: Radio Access for Third Generation Mobile Communications
Instruction buffering exploration for low energy VLIWs with instruction clusters
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
Facilitating the search for compositions of program transformations
Proceedings of the 19th annual international conference on Supercomputing
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
IEEE Computer Architecture Letters
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies
International Journal of Parallel Programming
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of a low power pre-synchronization ASIP for multimode SDR terminals
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Function inlining and loop unrolling for loop acceleration in reconfigurable processors
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
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Modern mobile devices need to be extremely energy efficient. Due to the growing complexity of these devices, energy aware design exploration has become increasingly important. Current exploration tools often do not support energy estimation, or require the design to be very detailed before the estimate is possible. It is important to get early feedback on both performance and energy consumption during all phases of the design and at higher abstraction levels. This paper presents a unified optimization and exploration framework, from source level transformation to processor architecture design. The proposed retargetable compiler and simulator framework can map applications to a range of processors and memory configurations, simulate and report detailed performance and energy estimates. An accurate energy modeling approach is introduced, which can estimate the energy consumption of processor and memories at a component level, which can help to guide the design process. Fast energy-aware architecture exploration is illustrated using an example processor. The flow is demonstrated using a representative wireless benchmark on two state of the art processors and on a processor with advanced low power extensions for memories. The framework also supports exploration of various novel low power extensions and their combinations. We show that a unified framework enables fast feedback on the effect of source level transformations of the application code on the final cycle count and energy consumption.