Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Introduction of local memory elements in instruction set extensions
Proceedings of the 41st annual Design Automation Conference
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Trade-offs in loop transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Playing the trade-off game: Architecture exploration using Coffeee
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register file partitioning and recompilation for register file power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
COFFEE: compiler framework for energy-aware exploration
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Register file partitioning and compiler support for reducing embedded processor power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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SDR enables cost-effective multi-mode terminals but still suffers from significant energy penalty when compared to dedicated hardware solutions. At system level, this energy bottleneck can be leveraged capitalizing on heterogeneous MPSOC platforms where specific engines are dedicated to classes of functions with similar computation characteristics and duty cycle. In burst-based communication as in IEEE802.11 or IEEE802.16, burst detection functions have high duty cycle and hence need an ultra low power implementation. Besides, programmability must be preserved to support multiplemodes. A low-power pre-synchronization ASIP is designed targeting the IEEE802.11a/g/n and IEEE802.16e synchronization at 20MHz input rate. Power simulations at gate-level show that an IEEE802.16e synchronization (20MHz) can be carried out with an average power of 15.86mW. This corresponds to an effective energy efficiency of 115.89MOPS/mW (32-bit equivalent operations).