Chip multiprocessor based on data-driven multithreading model

  • Authors:

  • Kyriakos Stavrou;Costas Kyriacou;Paraskevas Evripidou;Pedro Trancoso

  • Affiliations:

  • Department of Computer Science, University of Cyprus, Nicosia 1678, Cyprus.;Department of Computer Engineering, Frederick Institute of Technology, Nicosia 1036, Cyprus.;Department of Computer Science, University of Cyprus, Nicosia 1678, Cyprus.;Department of Computer Science, University of Cyprus, Nicosia 1678, Cyprus

  • Venue:
  • International Journal of High Performance Systems Architecture
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Although the dataflow model of execution, with its obvious benefits, has been proposed for a long time, it has not yet been successfully exploited. Nevertheless, as traditional systems have recently started to reach their limits in delivering higher performance, new models of execution that use dataflow-like concepts are being studied. Among these, Data-Driven Multithreading (DDM) is a multithreading model that effectively hides the communication delay and synchronisation overheads. In DDM threads are scheduled as soon as their input data has been produced, that is, in a dataflow-like way. In addition to presenting a motivation to the dataflow model of execution, this paper also presents an overview of the DDM project. In particular, it focuses on the Chip Multiprocessor (CMP) implementation using the DDM model, its hardware, run-time system and performance evaluation. The DDM-CMP inherits the benefits of both the DDM model which allows to overcome the memory wall limitation and the CMP which offers a simpler design, higher degree of parallelism and larger power-performance efficiency, therefore overcoming the power wall. Preliminary experimental results show a significant benefit in terms of both speedup and power consumption, making the DDM-CMP architecture an attractive architecture for future processors.