Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power and energy reduction via pipeline balancing
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
What is the limit of energy saving by dynamic voltage scaling?
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Joint local and global hardware adaptations for energy
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Compiler-Directed Dynamic Frequency and Voltage Scheduling
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
Proceedings of the 30th annual international symposium on Computer architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Energy-efficient instruction scheduling utilizing cache miss information
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
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We propose a novel hardware-based DVS technique called dynamic processor throttling (DPT) for power efficient computations. DPT focuses on the performance balance between the processor and main memory. When a performance imbalance is detected, DPT tries to redress the imbalance by setting the clock frequency and supply voltage of the processor to a well-balanced point. This paper describes the micro-architecture mechanisms of DPT and shows the evaluation results on energy saving and performance compared with a conventional cache-miss-driven DVS technique. The results reveal that DPT can reduce 17% of the energy with a 3.4% performance degradation and DPT surpasses the conventional technique in both performance and energy.