Software-cooperative power-efficient heterogeneous multi-core for media processing

Authors:
Hiroaki Shikano;Masaki Ito;Kunio Uchiyama;Toshihiko Odaka;Akihiro Hayashi;Takeshi Masuura;Masayoshi Mase;Jun Shirako;Yasutaka Wada;Keiji Kimura;Hironori Kasahara
Affiliations:
Hitachi, Ltd., Tokyo, Japan and Waseda University, Tokyo, Japan;Hitachi, Ltd., Tokyo, Japan;Hitachi, Ltd., Tokyo, Japan;Hitachi, Ltd., Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan;Waseda University, Tokyo, Japan
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Abstract

A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.