Compiler control power saving scheme for multi core processors

  • Authors:

  • Jun Shirako;Naoto Oshiyama;Yasutaka Wada;Hiroaki Shikano;Keiji Kimura;Hironori Kasahara

  • Affiliations:

  • Dept. of Computer Science;Dept. of Computer Science;Dept. of Computer Science;Advanced Chip Multiprocessor Research Institute, Waseda University, Tokyo, Japan;Dept. of Computer Science;Dept. of Computer Science

  • Venue:
  • LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
  • Year:
  • 2005

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Abstract

With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.