Hierarchical parallelism control for multigrain parallel processing

  • Authors:

  • Motoki Obata;Jun Shirako;Hiroki Kaminaga;Kazuhisa Ishizaka;Hironori Kasahara

  • Affiliations:

  • Dept. of Electrical, Electronics and Computer Engineering, Waseda University;Dept. of Electrical, Electronics and Computer Engineering, Waseda University;Dept. of Electrical, Electronics and Computer Engineering, Waseda University;Dept. of Electrical, Electronics and Computer Engineering, Waseda University;Dept. of Electrical, Electronics and Computer Engineering, Waseda University

  • Venue:
  • LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
  • Year:
  • 2002

Quantified Score

Hi-index 0.00

Visualization

Abstract

To improve effective performance and usability of shared memory multiprocessor systems, a multi-grain compilation scheme, which hierarchically exploits coarse grain parallelism among loops, subroutines and basic blocks, conventional loop parallelism and near fine grain parallelism among statements inside a basic block, is important. In order to efficiently use hierarchical parallelism of each nest level, or layer, in multigrain parallel processing, it is required to determine how many processors or groups of processors should be assigned to each layer, according to the parallelism of the layer. This paper proposes an automatic hierarchical parallelism control scheme to assign suitable number of processors to each layer so that the parallelism of each hierarchy can be used efficiently. Performance of the proposed scheme is evaluated on IBM RS6000 SMP server with 8 processors using 8 programs of SPEC95FP.