Parallelizing compiler framework and API for power reduction and software productivity of real-time heterogeneous multicores

Authors:
Akihiro Hayashi;Yasutaka Wada;Takeshi Watanabe;Takeshi Sekiguchi;Masayoshi Mase;Jun Shirako;Keiji Kimura;Hironori Kasahara
Affiliations:
Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan;Department of Computer Science and Engineering, Waseda University, Tokyo, Japan
Venue:
LCPC'10 Proceedings of the 23rd international conference on Languages and compilers for parallel computing
Year:
2010

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Abstract

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.