Proceedings of the Conference on Design, Automation and Test in Europe
Advanced system LSIs for home 3D system
Proceedings of the 16th Asia and South Pacific Design Automation Conference
LCPC'10 Proceedings of the 23rd international conference on Languages and compilers for parallel computing
| Hi-index | 0.00 |
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, hierarchical approaches from UniPhier Soc level, UniPhier Processor level, IPP (Instruction Parallel Processor) level, and Circuit level are adopted. As SoC level, 1) Well functionally isolated 5 major units of UniPhier SoC architecture, 2) Dedicated stream DMA controller which can minimize CPU load and memory access. As UniPhier Processor level, 1) UniPhier Processor consists of IPP with dedicated low power hardware engine, 2) VMP (Virtual Multi-Processor) mechanism with micro sleep which can reduce average power consumption in case of multiple tasks concurrent operation, 3) Intermittent operation with the combination of micro-sleep and clock/power down scheme in case of very light load operation. As IPP level, 1) Sophisticated instruction fetch buffer mechanism which can reduce more than 50% memory access for instruction fetch. 2) Hierarchical and selective clock gating scheme by detailed clock power analysis and clock activity rate analysis on real application,) Optimized physical implementation with low-power library and selective use of custom macros. As circuit level, mixed body bias technique with fixed Id and fixed Vt control which can realize 85 % delay variation suppressed and 25% ED product improvement compared with the No body bias.