Hybrid functional and instruction level power modeling for embedded processors

  • Authors:

  • Holger Blume;Daniel Becker;Martin Botteck;Jörg Brakensiek;Tobias G. Noll

  • Affiliations:

  • Chair for Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany;Chair for Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany;Nokia Research Center, Bochum, Germany;Nokia Research Center, Bochum, Germany;Chair for Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany

  • Venue:
  • SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
  • Year:
  • 2006

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Abstract

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.