Evaluation and choice of various branch predictors for low-power embedded processor

Authors:
DongRui Fan;HongBo Yang;GuangRong Gao;RongCai Zhao
Affiliations:
Institute of Computing Technology, The Chinese Academy of Sciences, Bejing 100080, P.R. China;Department of Electrical and Computer Engineering, University of Delaware, Newark, DE;Department of Electrical and Computer Engineering, University of Delaware, Newark, DE;Institute of Computing Technology, The Chinese Academy of Sciences, Bejing 100080, P.R. China
Venue:
Journal of Computer Science and Technology
Year:
2003

Citing 15
Cited 1

Two-level adaptive training branch prediction

MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Alternative implementations of two-level adaptive branch prediction

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Improving the accuracy of dynamic branch prediction using branch correlation

ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Speculative execution and branch prediction on parallel machines

ICS '93 Proceedings of the 7th international conference on Supercomputing
Cache design trade-offs for power and performance optimization: a case study

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Alternative implementations of hybrid branch predictors

Proceedings of the 28th annual international symposium on Microarchitecture
Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques

IEEE Transactions on Computers
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Very low power pipelines using significance compression

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors

IEEE Micro
A study of branch prediction strategies

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy

ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Power Issues Related to Branch Prediction

HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop

An energy efficient TLB design methodology

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power is an important design constraint in embedded computing systems. To meet the power constraint, microarchitecture and hardware designed to achieve high performance need to be revisited, from both performance and power angles. This paper studies one of them: branch predictor. As well known, branch prediction is critical to exploit instruction level parallelism effectively, but may incur additional power consumption due to the hardware resource dedicated for branch prediction and the extra power consumed on mispredicted branches. This paper explores the design space of branch prediction mechanisms and tries to find the most beneficial one to realize Iow-power embedded processor. The sample processor studied is Godson-like processor, which is a dual-issue, out-of-order processor with deep pipeline, supporting MIPS instruction set.