On load latency in low-power caches

Authors:
Soontae Kim;N. Vijaykrishnan;M. J. Irwin;L. K. John
Affiliations:
The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;The University of Texas at Austin, Austin, TX
Venue:
Proceedings of the 2003 international symposium on Low power electronics and design
Year:
2003

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Abstract

Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of non-determinism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.