A survey of process migration mechanisms
ACM SIGOPS Operating Systems Review
Empirical studies of competitve spinning for a shared-memory multiprocessor
SOSP '91 Proceedings of the thirteenth ACM symposium on Operating systems principles
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
Thermal-Aware Clustered Microarchitectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Proceedings of the 32nd annual international symposium on Computer Architecture
Network I/O Acceleration in Heterogeneous Multicore Processors
HOTI '06 Proceedings of the 14th IEEE Symposium on High-Performance Interconnects
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
ATEC '99 Proceedings of the annual conference on USENIX Annual Technical Conference
Accurate branch prediction for short threads
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Efficient operating system scheduling for performance-asymmetric multi-core architectures
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
The shared-thread multiprocessor
Proceedings of the 22nd annual international conference on Supercomputing
Amdahl's Law in the Multicore Era
Computer
OS execution on multi-cores: is out-sourcing worthwhile?
ACM SIGOPS Operating Systems Review
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
OS execution on multi-cores: is out-sourcing worthwhile?
ACM SIGOPS Operating Systems Review
ACM SIGOPS Operating Systems Review
Software data spreading: leveraging distributed caches to improve single thread performance
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Data marshaling for multi-core architectures
Proceedings of the 37th annual international symposium on Computer architecture
Improving server performance on multi-cores via selective off-loading of OS functionality
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
SST + gem5 = a scalable simulation infrastructure for high performance computing
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
When slower is faster: on heterogeneous multicores for reliable systems
USENIX ATC'13 Proceedings of the 2013 USENIX conference on Annual Technical Conference
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We address the software costs of switching threads between cores in a multicore processor. Fast core switching enables a variety of potential improvements, such as thread migration for thermal management, fine-grained load balancing, and exploiting asymmetric multicores, where performance asymmetry creates opportunities for more efficient resource utilization. Successful exploitation of these opportunities demands low core-switching costs. We describe our implementation of core switching in the Linux kernel, as well as software changes that can decrease switching costs. We use detailed simulations to evaluate several alternative implementations. We also explore how some simple architectural variations can reduce switching costs. We evaluate system efficiency using both real (but symmetric) hardware, and simulated asymmetric hardware, using both microbenchmarks and realistic applications.