Something old and something new: P-states can borrow microarchitecture techniques too

  • Authors:

  • Yasuko Eckert;Srilatha Manne;Michael J. Schulte;David A. Wood

  • Affiliations:

  • Advanced Micro Devices, Inc., Bellevue, WA, USA;Advanced Micro Devices, Inc., Portland, OR, USA;Advanced Micro Devices, Inc., Austin, TX, USA;University of Wisconsin - Madison, Madison, WI, USA

  • Venue:
  • Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
  • Year:
  • 2012

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Abstract

The limited utility of voltage scaling in nano-scale technologies has led high-performance processors to rely increasingly on frequency scaling for power management. However, frequency scaling provides only a linear dynamic power reduction. In this paper, we make a case for dynamically disabling performance optimizations, leveraging previously proposed low-power techniques, for more efficient power-performance trade-offs. By carefully selecting which optimizations to turn off, our lowest P-state consumes less than half the power achieved by frequency scaling, on average, for comparable performance. For all workloads, our approach performs as well or better than DVFS, demonstrating the effectiveness of our approach.