QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education

Authors:
Gregory J. Briggs;Edwin J. Tan;Nicholas A. Nelson;David H. Albonesi
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;Cornell University, Ithaca, NY
Venue:
WCAE '05 Proceedings of the 2005 workshop on Computer architecture education: held in conjunction with the 32nd International Symposium on Computer Architecture
Year:
2005

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Abstract

In this paper, we describe a graphic editing tool called QUILT (Quick Utility for Integrated circuit Layout and Temperature modeling). QUILT permits users to rapidly build floorplans of integrated circuits, providing both a visual aid as well as an input to the HotSpot simulator. The tool provides numerous features for estimating circuit performance, such as interconnect delay, and for generating graphical images for publications. As a graphical and easy to use tool, QUILT is well suited for both research and coursework purposes.