Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Quantifying hardware counter sampling error in computer system workload characterization
Quantifying hardware counter sampling error in computer system workload characterization
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Processing streaming media comprises several program phases (often distinct) that are periodic and independent of application data. In this paper we characterize execution of such programs into execution phases based on their dynamic IPC (Instruction Per Cycle) profile. We show that program execution of selected phases can be dynamically boosted by activating additional standby functional units which ae otherwise powered down for saving energy. Through simulation we show that speedup ranging from 1.1 to 1.25 can be achieved while reducing the energy-delay product (EDP) for most of the media benchmarks evaluated. Additionally we show that artificially introduced stalls during phases of processor underutilization reduces power by around 2 to 4%.