Hybrid-scheduling for reduced energy consumption in high-performance processors

Authors:
Madhavi Valluri;Lizy John;Heather Hanson
Affiliations:
Systems and Technology Group, IBM Corporation, Austin, TX;Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX;Electrical and Computer Engineering Department, The University of Texas at Austin, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

This paper develops a technique that uniquely combines the advantages of compile-time static scheduling and hardware dynamic scheduling to reduce energy consumption in dynamically scheduled processors. In this hybrid-scheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time bypass the dynamic scheduling hardware and execute in a low-power static mode. Experiments on several media and scientific benchmarks demonstrate that the proposed scheme can provide significant reduction in energy consumption with negligible performance degradation.