A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation

Authors:
Marco A. Ramirez;Adrian Cristal;Mateo Valero;Alexander V. Veidenbaum;Luis Villa
Affiliations:
Computer Architecture Department U.P.C. Spain;Computer Architecture Department U.P.C. Spain;Computer Architecture Department U.P.C. Spain;Dep. of Computer Science, University of California Irvine;Mexican Petroleum Institute
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.