HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support

  • Authors:

  • Yu-Ting Chen;Jason Cong;Glenn Reinman

  • Affiliations:

  • University of California, Los Angeles, Los Angeles, CA, USA;University of California, Los Angeles, Los Angeles, CA, USA;University of California, Los Angeles, Los Angeles, CA, USA

  • Venue:
  • CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2011

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Abstract

The configuration of L1 caches has a significant impact on the performance and energy consumption of an embedded system. Normally, an embedded system is designed for a specific application or a domain of applications. Performing simulations on the application(s) is the most popular way to find the optimal L1 cache configuration. However, the simulation-based approach suffers from long simulation time due to the need to exhaustively simulate all configurations, which are characterized by three parameters: the number of cache sets, associativity, and the cache line size. In previous work, the most time-consuming part was to determine the hit or miss status of a cache access under each configuration by performing a linear search on a long linked-list based on the inclusion property. In this work, we propose a novel simulator, HC-Sim, which adopts elaborate data structures, a centralized hash table, and a novel miss counter structure, to effectively reduce the search time. On average, we can achieve 2.56X speedup compared to the existing fastest approach (SuSeSim). In addition, we implement HC-Sim by using the dynamic binary instrumentation tool, Pin. This provides scalability for simulating larger applications by eliminating the overhead of generating and storing a huge trace file. Furthermore, HC-Sim provides the capacity to simulate an L1 cache and a scratchpad memory (SPM) simultaneously. It helps designers to explore the design space considering both L1 cache configurations and the SPM sizes.