Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture

• Authors: Arun Rangasamy;Rahul Nagpal;Y.N. Srikant
• Venue: Proceedings of the 5th conference on Computing frontiers
• Year: 2008

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain's frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection. Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies (used by online methods) and slack manifestation for a particular frequency setting (software based methods). We evaluate our method with subsets of SPECFP2000, Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique) in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands. Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.