The expandable split window paradigm for exploiting fine-grain parallelsim
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Dynamic zero compression for cache energy reduction
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Energy reduction in queues and stacks by adaptive bitwidth compression
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy: efficient instruction dispatch buffer design for superscalar processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Efficient dynamic scheduling through tag elimination
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A scalable instruction queue design using dependence chains
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A high-speed dynamic instruction scheduling scheme for superscalar processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Energy-efficient hybrid wakeup logic
Proceedings of the 2002 international symposium on Low power electronics and design
Instruction issue logic for pipelined supercomputers
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Complexity-effective superscalar processors
Complexity-effective superscalar processors
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Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for instruction wakeup, which uses a partitioned instruction queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.