HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
mlcache: A Flexible Multi-Lateral Cache Simulator
MASCOTS '98 Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
A generic system simulator with novel on-chip cache and throughput models for gigascale integration
A generic system simulator with novel on-chip cache and throughput models for gigascale integration
Making a Case for Efficient Supercomputing
Queue - Power Management
Memory in processor: a novel design paradigm for supercomputing architectures
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The onset of Deep Sub Micron (DSM) technology has driven the computing world towards billion device multi-GHz processor architectures leading to a stiff upward curve in power consumption and power density (W/cm2). In this paper we develop a graph-based power model for multiprocessors that predicts power requirements across the components of the cluster (Compute node, Memory and Network system) at various hierarchical levels when applications are run. PASCOM proposes new metrics for power measurement that integrates execution module characteristics with power dissipation metrics. The PASCOM model is applied to Memory In Processor chip and we study power consumption for parallel scientific applications from SPLASH2 and NAS Parallel suite. Total power dissipated varies by 15%. However, the static and dynamic power dissipation exhibit up to 33% and 60% variation respectively due to workload characteristics.