ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Tolerating latency through software-controlled data prefetching
Tolerating latency through software-controlled data prefetching
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Effective Hardware-Based Data Prefetching for High-Performance Processors
IEEE Transactions on Computers
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
ACM Transactions on Architecture and Code Optimization (TACO)
Energy-Constrained prefetching optimization in embedded applications
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Energy-efficient hardware data prefetching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Some traditional optimizations improve the performance of pro-cessors, but consume the higher power dissipation. We study this trade-off using software prefetching as performance-oriented optimization technique. We first demonstrate that software prefetching provides a significant performance boost with the higher power on several memory-intensive benchmarks. However, when we combine software prefetching with dynamic voltage/frequency scaling (DVFS), the performance gain can be achieved without power increase, which is called a power-aware approach. Besides reducing power dissipation through DVFS, we also improve the performance through adjusting the prefetch distance. A modified SimpleScalar/Wattch is used to evaluate our power-aware software prefetching. Experimental results show this optimization approach is effective to guarantee no power increase due to prefetching and improve the performance of software prefetching.