A method of redundant clocking detection and power reduction at RT level design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Clock gating effectiveness metrics: Applications to power optimization
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
| Hi-index | 0.00 |
Clock Gating has been the most widely used method to reduce dynamic power for digital designs. Increasingly the need to assess the quality of a clock gating implementation has resulted in generation of various benchmarking criteria. These criteria however fail to provide a feel to the designer about quality of a current implementation and the scope available for further clock gating. Prior work has also reported various datapath based clock gating techniques to optimize for dynamic power. In this paper we present a new approach to analyze this problem through the IO Exclusivity (IOEX) graphs and Cluster Efficiency (CE) plots. The IOEX graph captures the datapath activity across the sequential elements normalized to the source clock. This exercise produces sequential elemental clusters or modules, which are amenable to clock gating. A CE plot then provides a visual insight into these fine grained implementations to aid the designer to further gate the given cluster. This additional gating can then be implemented either at synthesis or at the layout stages, depending on the design cycle time. Results from 65nm designs show that up to 20% dynamic power savings can be achieved with our approach over and above the industry standard low power synthesis solutions.