Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
HybDTM: a coordinated hardware-software approach for dynamic thermal management
Proceedings of the 43rd annual Design Automation Conference
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Many-core design from a thermal perspective
Proceedings of the 45th annual Design Automation Conference
Accurate Temperature Estimation for Efficient Thermal Management
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Temperature control of high-performance multi-core platforms using convex optimization
Proceedings of the conference on Design, automation and test in Europe
A framework for predictive dynamic temperature management of microprocessor systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimizing Thermal Sensor Allocation for Microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Technology scaling has allowed integration of multiple cores into a single die. However, high power consumption of each core leads to very high heat density, limiting the throughput of thermal-constrained multi-core processors. To maximize the throughput, various software-based dynamic thermal management and optimization techniques have been proposed, many of which depend on accurate temperature sensing of each core. However, the decision for dynamic thermal management and throughput optimization only based on the temperature of each core can result in less optimal throughput in certain circumstances according to our investigation. In this paper, we propose 1) a dynamic power estimation method using a single thermal sensor for each core in multi-core processors, 2) a die temperature reconstruction method using the estimated power, and 3) a throughput optimization method based the estimated power instead of the temperature. According to our experiment using 90nm technology, the proposed method results in less than 3% error in estimating power and hot-spot temperature of a multi-core processor. Furthermore, the proposed throughput optimization method based on the estimated power leads to up to 4% higher throughput than a temperature-based optimization method.