Accurate on-line prediction of processor and memoryenergy usage under voltage scaling
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Koala: a platform for OS-level power management
Proceedings of the 4th ACM European conference on Computer systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accelerating embedded software power profiling using run-time power emulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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Numerous dynamic power management techniques have been proposed which utilize the knowledge of processor power/energy consumption at run-time. So far, no efficient method to provide run-time power/energy data has been presented. Current measurement systems draw too much power to be used in small embedded designs and existing performance counters can not provide sufficient information for run-time optimization. This paper presents a novel methodology to solve the problem of run-time power optimization by designing a processor that estimates its own power/energy consumption. Estimation is performed by the addition of small counters that tally events which consume power. This methodology has been applied to an existing processor resulting in an average power error of 2% and energy estimation error of 1.5%. The system adds little impact to the design, with only a 4.9% increase in chip area and a 3% increase in average power consumption. A case study of an application that utilizes the processor showcases the benefits the methodology enables in dynamic power optimization.