Power analysis of embedded software: a first step towards software power minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
The benefits of event: driven energy accounting in power-sensitive systems
EW 9 Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system
Hardware Accelerated Power Estimation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Power prediction for intel XScale® processors using performance monitoring unit events
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Run-time energy estimation in system-on-a-chip designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Accelerating system-on-chip power analysis using hybrid power estimation
Proceedings of the 44th annual Design Automation Conference
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Low-Impact Processor for Dynamic Runtime Power Management
IEEE Design & Test
Full-system chip multiprocessor power evaluations using FPGA-based emulation
Proceedings of the 13th international symposium on Low power electronics and design
An emulation-based real-time power profiling unit for embedded software
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
An instruction-level energy model for embedded VLIW architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power-aware software development of complex applications is frequently rendered infeasible by the extensive simulation times required for the power estimation process. In this paper, we propose a methodology for rapidly estimating the power profile of a given system based on high-level power emulation. By augmenting the HDL implementation of the system with a high-level power model, a power profile is generated during run-time. We evaluate our approach on a deep-submicron 80251-based smart-card microcontroller-system. The additional hardware effort for introducing the power emulation functionality is only 1.5% while the average estimation error is below 10% as compared to gate-level simulations.