Integrating functional and power simulation in embedded systems design
Journal of Embedded Computing - Low-power Embedded Systems
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
An emulation-based real-time power profiling unit for embedded software
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A precise high-level power consumption model for embedded systems software
EURASIP Journal on Embedded Systems
Accelerating embedded software power profiling using run-time power emulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Instruction-based energy estimation methodology for asymmetric manycore processor simulations
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
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In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a K-issue VLIW processor is O(N2K) where N is the number of operations in the ISA and K is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducing the complexity of the characterization problem to O(K×N 2). The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline