Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
The working set model for program behavior
Communications of the ACM
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Proceedings of the 30th annual international symposium on Computer architecture
Comparing Program Phase Detection Techniques
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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Asymmetric chip multiprocessors are imminent in the multi-core era primarily due their potential for power-performance efficiency. In order for software to fully realize this potential, the scheduling of threads to cores must be automated to adapt to the changing program behavior. However, strict system abstraction layers limit the controllability and observability of low level hardware details, thereby, limiting the state-of-the-art systems to rely on manual or static mapping of threads to cores in an asymmetric multi-core. In this paper, we propose a self-adaptive scheduler that exploits program behavior at runtime by matching computational demands of threads to the capabilities of cores. We present a novel empirical model to predict the selection of an appropriate core (based on optimizing throughput, power or performance per watt) for changing program phases within threads. Thread migration is initiated when an optimal mapping of threads to cores is predicted. Results show that our predictive schedulers for the three target optimizations are within 10% of the ideal scheduler.