Power-efficient and scalable load/store queue design via address compression

Authors:
Yi-Ying Tsai;Chia-Jung Hsu;Chung-Ho Chen
Affiliations:
National Cheng Kung University, Tainan, Taiwan;National Cheng Kung University, Tainan, Taiwan;National Cheng Kung University, Tainan, Taiwan
Venue:
Proceedings of the 2008 ACM symposium on Applied computing
Year:
2008

Citing 9
Cited 0

Address compression through base register caching

MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
SPEC CPU2000: Measuring CPU Performance in the New Millennium

Computer
Creating a wider bus using caching techniques

HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Scalable Hardware Memory Disambiguation for High ILP Processors

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Reducing Design Complexity of the Load/Store Queue

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Memory Ordering: A Value-Based Approach

Proceedings of the 31st annual international symposium on Computer architecture
Decomposing the load-store queue by function for power reduction and scalability

IBM Journal of Research and Development
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fully-associative CAM structure to search the address for collision and consequently poses scalability challenges of power consumption and area cost. Using the proposed approach, the LSQ can reduce the area cost ranging from 32% to 66% and power consumption ranging from 38% to 71%, depending on the compression parameter. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at an optimal configuration.