Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Thermal-Aware Clustered Microarchitectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Balance of Power: Dynamic Thermal Management for Internet Data Centers
IEEE Internet Computing
Monitoring Temperature in FPGA based SoCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Challenges of data center thermal management
IBM Journal of Research and Development - POWER5 and packaging
Making scheduling "cool": temperature-aware workload placement in data centers
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
ATC'07 2007 USENIX Annual Technical Conference on Proceedings of the USENIX Annual Technical Conference
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
Totally green: evaluating and designing servers for lifecycle environmental impact
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Design configuration selection for hard-error reliable processors via statistical rules
Microprocessors & Microsystems
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Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling resources, especially in large-scale systems where cooling power can be 50~100% of IT power. Further, the efficiency of cooling solutions degrade non-linearly with supply temperature. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots. Applying current to a superlattice TEC-film that is deposited between silicon and the heat spreader results in a Peltier effect, which spreads the heat and lowers the temperature of the hot-spot significantly and improves chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sour-ces, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multi-scale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save ~27% cooling power on average while providing the same processor reliability as a data center running at 288K.