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In this paper, we propose Selective Word Reading (SWR) technique for a low power processor without a loss of performance. The development of this technique was motivated by the differences between store unit sizes per storage level. In typical cases, the CPU register stores data with a unit size of one word, the L1 cache stores data using a unit size of four words and the L2 cache stores with a unit size of eight words. In SWR, only the necessary part of the block is activated during the cache access process. Therefore, the L1 cache controller reads one word from the L1 cache, which uses a unit size of four words, and the L2 cache controller reads four words from the L2 cache, which uses a unit size of eight words. The proper numbers of mats in a sub-bank must be chosen for the highest SWR best efficiency. For a four-way set associative L1 cache with a size of 32kB, a block size of 32B and four mats per sub-bank, SWR accomplishes dynamic energy savings of 67.54% without considering the leakage energy and 56.75% when the leakage energy is considered with no performance degradation and negligible area reduction. Additionally, with a 16-way set associative L2 cache with a size of 1MB, a block size of 64B and eight mats per sub-bank, SWR accomplishes dynamic energy savings of 60.41% for the cache overall before the leakage energy is considered and 11.71% after.