Hierarchical memory system design for a heterogeneous multi-core processor

Authors:
Jianjun Guo;Mingche Lai;Zhengyuan Pang;Libo Huang;Fangyuan Chen;Kui Dai;Zhiying Wang
Affiliations:
National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China
Venue:
Proceedings of the 2008 ACM symposium on Applied computing
Year:
2008

Citing 14
Cited 1

MOVE: a framework for high-performance processor design

Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Reducing TLB power requirements

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Designing high bandwidth on-chip caches

Proceedings of the 24th annual international symposium on Computer architecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The Stanford Hydra CMP

IEEE Micro
Generating physical addresses directly for saving instruction TLB energy

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Proceedings of the 31st annual international symposium on Computer architecture
Power Efficient Processor Architecture and The Cell Processor

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Logic-based eDRAM: origins and rationale for use

IBM Journal of Research and Development - Electrochemical technology in microelectronics
Memory hierarchy design for stream computing

Memory hierarchy design for stream computing
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design

ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
A heterogeneous multi-core processor architecture for high performance computing

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture

Partitioned scheduling for real-time tasks on multiprocessor embedded systems with programmable shared srams

Proceedings of the tenth ACM international conference on Embedded software

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multi-core architecture has become hot issue recently both for performance and power consideration. Memory system is the bottleneck under this circumstance. A multi-core architecture using simple cores based on transport triggered architecture is proposed. This architecture has a uniform programming view. The memory system design exploration and optimization is done and a hierarchical memory system is designed. A balanced memory bandwidth is provided to the multi-core architecture.