A heterogeneous multi-core processor architecture for high performance computing

Authors:
Jianjun Guo;Kui Dai;Zhiying Wang
Affiliations:
School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China;School of Computer, National University of Defense Technology, Changsha, Hunan, China
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

The increasing application demands put great pressure on high performance processor design. This paper presents a multi-core System-on-Chip architecture for high performance computing. It is composed of a sparcv8-compliant LEON3 host processor and a data parallel coprocessor based on transport triggered architecture, all of which are tied with a 32-bit AMBA AHB bus. The LEON3 processor performs control tasks and the data parallel coprocessor performs computing intensive tasks. The chip is fabricated in 0.18um standard-cell technology, occupies about 5.3mm2 and runs at 266MHz.