Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

  • Authors:

  • Kenzo Van Craeynest;Aamer Jaleel;Lieven Eeckhout;Paolo Narvaez;Joel Emer

  • Affiliations:

  • Ghent University, Ghent, Belgium;Intel Corporation, VSSAD, Hudson, MA;Ghent University, Ghent, Belgium;Intel Corporation, VSSAD, Hudson, MA;Intel Corporation, VSSAD, Hudson, MA and MIT, Cambridge, MA

  • Venue:
  • Proceedings of the 39th Annual International Symposium on Computer Architecture
  • Year:
  • 2012

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Abstract

Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The effectiveness of heterogeneous multi-cores depends on how well a scheduler can map workloads onto the most appropriate core type. In general, small cores can achieve good performance if the workload inherently has high levels of ILP. On the other hand, big cores provide good performance if the workload exhibits high levels of MLP or requires the ILP to be extracted dynamically. This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance. PIE collects CPI stack, MLP and ILP profile information, and estimates performance if the workload were to run on a different core type. Dynamic PIE adjusts the scheduling at runtime and thereby exploits fine-grained time-varying execution behavior. We show that PIE requires limited hardware support and can improve system performance by an average of 5.5% over recent state-of-the-art scheduling proposals and by 8.7% over a sampling-based scheduling policy.