Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
Thread scheduling for heterogeneous multicore processors using phase identification
ACM SIGMETRICS Performance Evaluation Review
Phase-based tuning for better utilization of performance-asymmetric multicore processors
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)
Proceedings of the 39th Annual International Symposium on Computer Architecture
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Heterogeneous multicore processors (HMPs) can provide better performance and reduced energy consumption than homogeneous ones [3]. Differences between cores provide different processing capabilities for different applications; a dynamic scheduler can exploit these differences to maximize performance and minimize energy consumption [5, 6] by adapting to fine changes in programs behavior. This work proposes new fine-grained online HMP schedulers using program phase identification. However, exploiting fine-grained scheduling results in frequent thread migrations that can harm performance. OS context switching is time consuming (30-60μs [4]). To reduce context switching overhead, a context switching circuit that both accelerates thread switches among cores in HMPs and reduces switching cost within each core (multitasking) is introduced.