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A light-weight fairness mechanism for chip multiprocessor memory systems
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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Aérgia: exploiting packet latency slack in on-chip networks
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ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache
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Energy efficiency for large-scale MapReduce workloads with significant interactive analysis
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A high performance adaptive miss handling architecture for chip multiprocessors
Transactions on High-Performance Embedded Architectures and Compilers IV
DIEF: an accurate interference feedback mechanism for chip multiprocessor memory systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Reliability-aware core partitioning in chip multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Probabilistic modeling for job symbiosis scheduling on SMT processors
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CRQ-based fair scheduling on composable multicore architectures
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Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)
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Staged memory scheduling: achieving high performance and scalability in heterogeneous systems
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Probabilistic shared cache management (PriSM)
Proceedings of the 39th Annual International Symposium on Computer Architecture
The dynamic granularity memory system
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Scalability-based manycore partitioning
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Per-thread cycle accounting in multicore processors
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Understanding fundamental design choices in single-ISA heterogeneous multicore architectures
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ADAPT: A framework for coscheduling multithreaded programs
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MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems
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Proceedings of the 40th Annual International Symposium on Computer Architecture
Resilient die-stacked DRAM caches
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PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Fairness-aware scheduling on single-ISA heterogeneous multi-cores
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization
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REF: resource elasticity fairness with sharing incentives for multiprocessors
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Assessing the performance of multiprogram workloads running on multithreaded hardware is difficult because it involves a balance between single-program performance and overall system performance. This article argues for developing multiprogram performance metrics in a top-down fashion starting from system-level objectives. The authors propose two performance metrics: average normalized turnaround time, a user-oriented metric, and system throughput, a system-oriented metric.