The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Symbiotic jobscheduling for a simultaneous multithreaded processor
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
The Impact of Resource Partitioning on SMT Processors
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Proceedings of the 18th annual international conference on Supercomputing
SWIFT: Software Implemented Fault Tolerance
Proceedings of the international symposium on Code generation and optimization
Cooperative cache partitioning for chip multiprocessors
Proceedings of the 21st annual international conference on Supercomputing
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Partitioning Multi-Threaded Processors with a Large Number of Threads
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
A Framework for Providing Quality of Service in Chip Multi-Processors
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Fault-Tolerance CMP Architecture based on SMT Technology
IMSCCS '07 Proceedings of the Second International Multi-Symposiums on Computer and Computational Sciences
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
A Redundancy Mechanism under Single Chip Multiprocessor Architecture
SEC '08 Proceedings of the 2008 Fifth IEEE International Symposium on Embedded Computing
Mixed-mode multicore reliability
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Algorithm-based fault tolerance applied to high performance computing
Journal of Parallel and Distributed Computing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A case for integrated processor-cache partitioning in chip multiprocessors
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Energy-efficient real-time scheduling of multimedia tasks on multi-core processors
Proceedings of the 2010 ACM Symposium on Applied Computing
Characterizing the soft error vulnerability of multicores running multithreaded applications
Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Power and performance aware reconfigurable cache for CMPs
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
Quantifying Thread Vulnerability for Multicore Architectures
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
Platform synthesis and partitioning of real-time tasks for energy efficiency
Journal of Systems Architecture: the EUROMICRO Journal
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Executing multiple applications concurrently is an important way of utilizing the computational power provided by emerging chip multiprocessor (CMP) architectures. However, this multiprogramming brings a resource management and partitioning problem, for which one can find numerous examples in the literature. Most of the resource partitioning schemes proposed to date focus on performance or energy centric strategies. In contrast, this paper explores reliability-aware core partitioning strategies targeting CMPs. One of our schemes considers both performance and reliability objectives by maximizing a novel combined metric called the vulnerability-delay product (VDP). The vulnerability component in this metric is represented with Thread Vulnerability Factor (TVF), a recently proposed metric for quantifying thread vulnerability for multicores. Execution time of the given application represents the delay component of the VDP metric. As part of our experimental analysis, proposed core partitioning schemes are compared with respect to normalized weighted speedup, normalized weighted reliability loss and normalized weighted vulnerability delay product gain metrics for various workloads of benchmark applications.