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Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
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This paper investigates the problem of partitioning a shared cache among threads executing in a Chip Multi-Processor (CMP). We propose Reconfigurable Cache for CMPs (ReCaC), a low-overhead run-time mechanism that dynamically partitions the cache based on the phase behavior of threads. Unlike the previously proposed performance aware partitioning approaches, ReCaC targets to use a minimum number of ways to trade-off between power and performance. ReCaC dynamically reverts back to a performance centric cache partitioning scheme if the power savings are not achievable. Our results show that in a 2-core architecture ReCaC saves on average 51.5% power in a L2 cache, which corresponds to 11.5% power savings of the processor chip and the memory. The overall processor energy efficiency is improved by up to 13.6%, achieving on average 8.5%. ReCaC proves to be scalable, saving on average 10.8% and 12.5% of the processor chip and memory power in 4-and 8-core architectures, respectively.