Fault-Tolerance CMP Architecture based on SMT Technology

  • Authors:

  • Linzhi Ning;Wenbin Yao;Jun Ni;Nianmin Yao

  • Affiliations:

  • -;-;-;-

  • Venue:
  • IMSCCS '07 Proceedings of the Second International Multi-Symposiums on Computer and Computational Sciences
  • Year:
  • 2007

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Abstract

In order to improve the reliability of the single-chip multi-processor (CMP), this paper proposes a fault- tolerant CMP architecture which combines with the Simultaneous Multi-threading (SMT) technology so as to implement the transient fault detection and to automatically accomplish the thread-level recovery. The architecture, through adopting a simple strategies and a little extra hardware to implement the functionality of fault tolerance, attains a wider coverage of the fault and improves the performance of the fault-tolerant CMP. Keywords: CMP, SMT, fault tolerance, thread