Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
Migration in Single Chip Multiprocessors
IEEE Computer Architecture Letters
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
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This work argues that, in the face of growing thermal constraints, under an increasing number of scenarios the most effective tiled processor design is one that can support efficient flashcrowding: in a nutshell, placing on a chip far more computational power than it can sustain for extended periods of time, and concentrating computation into a few transient hotspots.