Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Novel task migration framework on configurable heterogeneous MPSoC platforms
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An Evaluation of Vectorizing Compilers
PACT '11 Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
Benchmarking modern multiprocessors
Benchmarking modern multiprocessors
Vapor SIMD: Auto-vectorize once, run everywhere
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores
Proceedings of the First International Workshop on Code OptimiSation for MultI and many Cores
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Functionally Asymmetric Multi-Processor (FAMP) design represents a tradeoff between the programmability of a symmetric multi-processor and the exploitation of the workload heterogeneity of multi-processor system-on-chip. The functional asymmetry's management is a crucial issue in finding the potential power efficiency of the FAMP design. In this work-in-progress we propose a FAMP power model and extract some guidelines that take advantage of the asymmetric design. By analysing the behaviour of a SIMD hardware extension on the PARSEC benchmark suite, we show that the workload exhibits interesting hardware extension utilisation properties. In order to fit FAMP architectures, classical compilation/execution models, which are very efficient for symmetric multi-core, must be re-engineered.