Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Block alignment in 3D floorplan using layered TCG
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Handbook of Approximation Algorithms and Metaheuristics (Chapman & Hall/Crc Computer & Information Science Series)
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
General floorplans with L/T-shaped blocks using corner block list
Journal of Computer Science and Technology
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D integration for energy efficient system design
Proceedings of the 48th Design Automation Conference
IEEE Transactions on Evolutionary Computation
Arbitrary convex and concave rectilinear block packing using sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assembling 2-D Blocks Into 3-D Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The reuse of predesigned intellectual property (IP) blocks is critical for the commercial success of three-dimensional (3D) electronic circuits. In practice, IP blocks can be specified as rectangular as well as rectilinear 2D blocks. The 3D equivalent of 2D rectilinear blocks, orthogonal polyhedra, may be utilized for modeling tightly interconnected (sub-)modules placed onto adjacent dies or for design automation of versatile 3D-integrated systems. Such complex block geometries have not been adequately considered until now. We propose a new 3D layout representation that enables native 3D floorplanning of complex-shaped 3D blocks, i.e., orthogonal polyhedra spread onto multiple dies. Furthermore, it can also be applied during 3D floorplanning of both rectangular and rectilinear 2D blocks. In the former case, experiments reveal superior estimated wirelength and packing density compared to previous work.