Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as technology advances into the deep submicron era. 3D chip is a feasible solution to these problems. It has been shown that interconnect lengths can be greatly reduced in 3D ICs. In this paper, a novel 3D floorplan representation namely Layered Transitive Closure Graph (LTCG) is proposed, which is based on the Transitive Closure Graph (TCG) representation for 2D non-slicing floorplans. In LTCG, we can impose topological relationships between both blocks of the same layer and blocks of different layers. Experimental results have shown that LTCG is very promising for multi-layer floorplanning and can handle the inter-layer alignment problem effectively.