TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

Authors:
Moongon Jung;Joydeep Mitra;David Z. Pan;Sung Kyu Lim
Affiliations:
Georgia Institute of Technology GA;University of Texas at Austin TX;University of Texas at Austin TX;Georgia Institute of Technology GA
Venue:
Communications of the ACM
Year:
2014

Citing 6
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Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

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Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

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Abstract

Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously affect performance, leakage, and reliability of circuits. In this paper, we discuss an efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermomechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.