Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Through-silicon vias enable next-generation SiGe power amplifiers forwireless communications
IBM Journal of Research and Development
Co-design of signal, power, and thermal distribution networks for 3D ICs
Proceedings of the Conference on Design, Automation and Test in Europe
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
3D integration for energy efficient system design
Proceedings of the 48th Design Automation Conference
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Proceedings of the International Conference on Computer-Aided Design
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Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC) based liquid cooling. In case of power delivery, a highly complex power distribution network is required to deliver currents reliably to all parts of the 3D stacked IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because the signal, power, and thermal interconnects are all competing for routing space. In this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3D stacked ICs based on design of experiments (DOE) and response surface method (RSM). The goal is to improve performance, thermal, noise, and congestion metrics with our holistic approach. We also provide in-depth comparison between T-TSV and MFC based cooling method and discuss how to employ DOE and RSM to best co-optimize the multi-functional interconnects simultaneously.