IEEE Transactions on Computers
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Efficient checker processor design
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Performance improvement with circuit-level speculation
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
Designing the M·CORETM M3 CPU Architecture
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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A novel technique for improving the energy efficiency of microprocessors is disclosed. This new method relies on a fault-tolerance mechanism for timing violations, based on a speculative execution technique. Since power reduces quadratically with supply voltage, supply voltage reductions can result in substantial power savings. However, these reductions also cause a longer gate delay, and so the clock frequency must be reduced so that timing constraints of critical paths are not violated. If any fault-tolerance mechanism is provided for timing faults, it is not necessary to maintain the constraints. From these observations, we propose a fault-tolerance technique for timing violations, that efficiently utilizes the speculative execution mechanism and reduces power consumption. We call the technique constructive timing violation. The present study evaluated our proposal regarding this technique using a cycle-by-cycle simulator and determined the technique's efficiency regarding energy consumption.