Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique

Authors:
B. Chung;J. B. Kuo
Affiliations:
School of Eng Science, SFU, Burnaby, Canada;School of Eng Science, SFU, Burnaby, Canada
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold – high Vth for good standby power and low Vth for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.