Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique

Authors:
Henry X. F. Huang;Steven R. S. Shen;James B. Kuo
Affiliations:
Circuits, Devices and Systems Laboratory, School of Computer & Information Engineering, Peking University, Shenzhen Graduate School, Shenzhen, China;Circuits, Devices and Systems Laboratory, School of Computer & Information Engineering, Peking University, Shenzhen Graduate School, Shenzhen, China;Circuits, Devices and Systems Laboratory, School of Computer & Information Engineering, Peking University, Shenzhen Graduate School, Shenzhen, China
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

This paper describes a straightforward cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing highspeed low-power SOC applications using MTCMOS technique. The CBLPRP methodology is based on the cell swapping priority depending on the total leakage power reduction for a cell changing from LVT type to HVT type. Experimental results show that by employing CBLPRP Methodology on the ISCAS benchmark circuits, a 10-20% reduction in the leakage power consumption could be achieved as compared to the one using the GDSPOM technology.